1. Field of the Invention
The present invention relates to a monitor circuit for a performance of an LSI (Large Scale Integrated Circuit).
2. Description of Related Art
Recently, a demand for a reduction in power consumption of a processor has been increasing more than ever. An increase in power consumption causes a rise of a temperature of an LSI, and has a negative influence on reliability of the processor such as a service lifetime thereof. In addition, the increase in power consumption may cause other problems. For example, because of the increased power consumption, the power consumption may reach close to the limit of a power supply system.
As a technique for reducing the power consumption of the processor, a clock gating or a data gating is known. These techniques may be implemented within the processor. The clock gating or the data gating stops or slows down the operation of unnecessary logic circuits. However, because of an increase in CLK frequency or in the number of processor cores in the processor for further performance improvement, it may become more difficult to reduce the power consumption with the clock gating or the data gating.
In this respect, dynamic voltage frequency scaling (DVFS) disclosed in Non-Patent Document 1 or the like has been proposed in recent years. In DVFS, a power drop or a temperature change is monitored, and a power supply voltage and an operating frequency are controlled. Thereby, the operation of the processor is dynamically and flexibly changed so that the monitored amount cannot become an amount that influences reliability or reaches the limit of the power supply capacity. In this way, the power consumption is controlled below a critical value in DVFS (an example of a circuit diagram is shown in FIG. 8).
In addition, Non-Patent Document 2 discloses a technique of controlling a system in accordance with a performance of the system by installing a performance monitor. The system to be monitored includes a delay margin. This performance monitor is configured to monitor whether data may be accurately acquired in flip-flops (FF) within the delay margin (an example of a circuit diagram is shown in FIG. 9). In addition, as a monitor used in general, a ring oscillator circuit as shown in Patent Document 1, for example, is known (an example of a circuit diagram is shown in FIG. 10).
[Non-Patent Document 1] James Tschanz, Nam Sung Kim, Saurabh Dighe, et. al., “Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature and Aging,” ISSCC Dig. Tech. Papers, February, 2007.
[Non-Patent Document 2] Alan Drake, Robert Stranger, Harmander Deogun, et. al., “A Distributed Critical-Path Timing Monitor for a 65 nm High Performance Microprocessor,” ISSCC Dig. Tech. Papers, February, 2007.
[Patent Document 1] Japanese Patent Application Publication No. 61-041976